Supermicro announced a KV cache storage solution with IBM and NVIDIA on November 5, 2026, designed to move reusable AI ...
Like virtual memory lets an OS use more RAM than it physically has, CMV lets Claude Code use more context than fits in one session — by snapshotting, branching, and trimming the understanding your ...
On August 7, I wrote a paid article titled 'Which of the 5 Memory Companies Is Truly Strong?' Since the financial results for all memory companies were mostly released by the end of October, I checked ...
A newly published hybrid index structure combines an adaptive radix tree with a hash-based skip list to cut deep-key lookup ...
At OCP 2026, Samsung and SK hynix both detailed strategies for addressing the memory demands of agentic AI’s key-value cache workloads, with coverage framing the announcements as further evidence that ...
AI is running on home PCs.If so, does that mean massive data centers and expensive HBM will no longer be needed?When holding memory stocks, even news about things becoming "more convenient" makes me a ...
Micron expects higher HBM pricing in calendar 2027 to narrow its margin gap with conventional DRAM. But the long-term test is ...
The 5th GMIF Innovation Summit (Global Memory Innovation Forum 2026, GMIF2026), co-hosted by the Shenzhen Memory Industry Association (SMIA) and the School of Integrated Circuits at Peking University, ...
ST's HELIX research program with NUS will explore how memory, processing and software can be designed together for real-time embedded AI.
CXL computational memory chip maker XCENA secured back-to-back commercial commitments from SK Hynix and Samsung at OCP Global Summit 2026: SK Hynix launched CXL Hybrid Memory, its first named product ...
As the volume of data handled by AI grows explosively, data bottlenecks have emerged as a new challenge. Can next-generation memory technology offer the solution? There is now an opportunity to hear ...
D Stacked DRAM, SK Hynix’s next-generation AI memory architecture bonding DRAM directly onto processor dies via Through-Silicon Via interconnects, was formally disclosed at SEDEX 2026 on October 14.
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